1. Field of the Invention
The present invention relates to access techniques for a sequential access memory or an FIFO memory.
2. Description of the Background Art
One of the background arts, which is disclosed in Japanese Patent Laid-Open Gazette 52-154311, is an FIFO queue control system having a storage region of ring configuration in which a ring counter of N cycle is used as write pointer and read pointer.
Another background art, which is disclosed in Japanese Patent Laid-Open Gazettes 63-27055 and 61-139990, is a word line selection system using a shift register.
Both of the above background arts, however, disclose only a word line selection which is achieved by using a shift register or a counter.
As a method to control the practical amount of memory of the FIFO memory in accordance with input, a FULL-flag control circuit and an EMPTY-flag control circuit are used in the above configuration. For example, in a single scanning period (1H Line) of 480 words, the setting of a FULL-flag at the 384-word point is detected. In this method, there arises some problems: When an address pointer using a shift register is employed, it is necessary to provide a comparator circuit to make a comparison every line between a word line for reading and a word line for writing. When a memory address counter is employed to make access to a DRAM, it is necessary to additionally provide two counters for reading and for writing to specify a location of the word line and a comparator circuit to compare the two counters. For these reasons, it is not desirable to use such circuits because of an increase in circuit scale.